Description Chips Talk, We Listen proteanTecs is a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital world built for autonomous driving, cloud computing, and AI, we depend on computing systems daily. But how can we guarantee their safety, reliability and functionality? proteanTecs is the first-ever company to provide visibility into next-gen chips while they are operating, based on the power of on-chip monitoring, machine learning, and data analytics. Here at proteanTecs, you'll be part of a team that's unlocking deep insights to make electronics more reliable, efficient, and high-quality. We're trusted by industry leaders in data centers, automotive, communications, and consumer devices – we work with the world's largest and most notable companies in tech.
Supportive company culture: Learn from the best. Our 200+ team members are experts in their field with a proven track record of success, and they're committed to fostering a collaborative and supportive work environment. International presence: We're a multinational company with a diverse team across multiple locations around the globe. You'll collaborate on projects with international impact, gaining a global perspective of the tech industry.
proteanTecs is looking for a Senior Logic Design Engineer to join the ride as we spearhead the next revolution in electronics and lead the IP Integration Enablement.
Lead and define how the proteanTecs Hardware IP is integrated into customer chips, ensuring a seamless and streamlined experience. As the IP Integration Enablement Lead, you will bridge R&D and customer perspectives—translating complex IP features into intuitive, low-touch integration flows and best practices. Your work will empower Application Engineers and customers alike, driving successful adoption and smooth deployment of Proteus IP across diverse chip segments. Key Responsibilities Customer-Centric Integration Leadership Act as the “voice of the customer” in internal R&D reviews, advocating for integration simplicity, design compatibility, and customer usability. Identify and address integration challenges early in the development cycle to ensure seamless adoption by customer design teams. Integration Infrastructure & Collateral Define and oversee all integration-related deliverables, ensuring quality, consistency, and alignment with customer integration needs.
o Lint, CDC, RDC and IPXACT views o Register maps, ICL and PDL files o Simulation and emulation views o Integration testbenches and verification collaterals Out-of-the-Box Integration Benchmark & Regression
Provide expert support for complex integration challenges escalated through the field teams. Gather structured feedback from Application Engineers and customers to continuously refine integration methodologies and improve the overall integration experience.
Requirements B.Sc. or M.Sc. in Electrical or Computer Engineering. 7+ years of experience in ASIC/SoC design or integration, with proven ownership of IP-level or subsystem integration. Strong background in RTL design, handoff methodologies and signoff tools (Lint, CDC, etc.). Proficiency in scripting (Python or equivalent) for flow automation. Experience with System-Verilog and simulation environments for integration validation. Strong interpersonal and communication skills, with the ability to represent R&D in customer-facing contexts. Advantages Experience with embedded monitoring or telemetry IPs. Familiarity with proteanTecs or similar silicon lifecycle monitoring technologies. Experience in chip-level bring-up or post-silicon validation. Familiarity with IP packaging standards (e.g., IPXACT) and deliverable generation.
Responsibilities None Personal skills None
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